Inlaid metal interconnect processes for semiconductor manufacturing are replacing conventional blanket metal deposition and etch processes. Traditionally, a blanket metal film has been deposited and patterned using photolithographic techniques to form a patterned metal interconnect. As metal geometries decrease and as metal lines are formed closer and closer together, it becomes more difficult to accurately pattern the metal lines and form the metal interconnects using a traditional blanket deposition and patterning process. Inlaid metal interconnect processes have been developed to overcome some of these problems. In an inlaid metal interconnect process, an interlayer dielectric (ILD) metal is deposited, and a via or opening is formed in this dielectric layer. A blanket layer of metal is then deposited across the device, including in the via. The blanket metal layer is then polished back, leaving metal only in the via area.
A dual inlaid interconnect process is an improvement over the single inlaid process in that both the metal via and the metal interconnect can be formed with the same metal deposition step. In a typical dual inlaid process, a first ILD material is deposited. A thin etchstop layer is deposited on this first ILD. A second ILD material is then deposited on the etchstop layer. Within this dielectric stack, both a via opening and a trench opening are formed, wherein the via opening is used to interconnect one metal layer to another, while the trench opening is used to form the metal interconnect.
There are at least three known processes for forming the openings in the ILD stacks in dual inlaid applications. In a first process, the intervening etchstop layer is patterned to form an opening in the etchstop which corresponds to the via opening. After forming the second or upper most ILD, a resist mask is deposited and patterned to match a pattern of the trenches. The ILD is then etched with the resist mask in place to form the trench, and a long overetch is performed to etch the underlying or first ILD using the patterned etchstop layer as an etch mask. However, a problem with this approach is that the extent of overetch necessary to clear the via often erodes the etchstop material around the vias and results in blown out vias. In an extreme case, adjacent vias may be eroded to the extend that they short together. Accordingly, the process is not suited for tight geometries.
A second known process for patterning the ILD stacks in a dual inlaid application is to form the via first and the trench or channel last. In such a process, the first or lower ILD layer, the etchstop layer, and the upper or second ILD layer are sequentially deposited. A resist mask is deposited on the device and patterned to match the via pattern. A via etch is then performed which etches the upper or second ILD layer and the etchstop layer and the lower or first ILD layer all within the same etch step. (The etch chemistry may or may not be changed to etch the etchstop layer in forming the via). Following the via etch, the first resist mask is removed, and a second resist mask is deposited and patterned to match the trench pattern. A second etch is performed to remove the upper most ILD layer to form the trench, wherein the etch is performed selectively to the etchstop layer. Because there is no need to perform an overetch to clear the oxide in the via portion in the first or lower most ILD layer, erosion of the etchstop around the via is minimized. However, a problem in forming the via first is that the aspect ratio (wherein the via is formed through the upper most ILD, the etchstop, and the lower most ILD) that will be created makes the via/trench etch very difficult. Accordingly, this process is not very scaleable as via dimensions become smaller. Furthermore, this process sequence often leaves a residue of the ILD material in the via, resulting in poor contact reliability.
The third known process for forming the dual inlaid structure involves forming the trench first and the via last. Again, in this process, the full dielectric stack is formed through sequential depositions of the first ILD layer, the etchstop layer, and the second ILD layer. A resist mask is then deposited and patterned according to the trench pattern. The upper most ILD layer is then etched using this resist mask to form the trenches. The resist mask is then removed, and a second resist mask is formed on the device, wherein the second resist mask is deposited and patterned to define the via pattern. After the second resist mask is patterned, the etchstop layer and the first ILD layer are etched with the second resist mask in place to form the vias. While in forming the trench first, a long overetch of either of the ILDs is avoided, and the aspect ratio of the via etch is reduced in comparison to forming the via first, it is very difficult to deposit and pattern the second resist mask. Because the second resist mask is defining the via pattern, this resist mask must be deposited into the trench openings formed in the second ILD layer. Accordingly, the resist will be unusually thick within the trench portion of the second ILD layer. It is difficult to accurately pattern such a thick mask with existing photolithographic equipment due to the limitations on the depth of focus.
Accordingly, there is a need in the semiconductor industry for a method to form a dielectric material and corresponding openings therein for inlaid metal applications which overcome the problems mentioned above. Furthermore, it would be desirable if such a method could be implemented with adding minimal processing steps and which can be easily integrated into a manufacturer's existing process.